In the increase of the device density on a chip, the metal interconnections also increases and occupy a large portion of the area of the chip. As a result, interconnection-related propagation delays occur more frequently with the increasing amounts of the interconnections within the limited area of the chip. To address this issue is using a multilevel interconnection scheme where interconnections are made through vias in the different dielectric layers isolating various levels of the interconnections. For the implementation of such a scheme, it is important that each level be well planarized so as to make vertical interconnections through lithography and patterning process.
Chemical mechanical planarization (CMP) is a common technique for polishing and thus planarizing the surface of a wafer using chemical slurries and mechanical abrasion. The CMP process is normally used to planarize copper metallization performed over the surface of the wafer, so that only copper deposited inside contact and via openings for interconnects remains. To succeed in conducting the CMP process, a good post-chemical mechanical planarization cleaning process is important. A popular method for the cleanup is to scrub the polished surface with a diluted chemical solution, such as alkaline solutions which remove particles effectively.
On the other hand, Low k dielectric layers are one of the promising candidates for isolating various levels of interconnections. However, in spite of their excellent electrical properties like k-value, leakage current and break down voltage, some of material properties of the low k dielectric layers, e.g., being hydrophilic and porous, result in metal ions from post-chemical mechanical planarization cleaning process attached on surfaces of the dielectric layers. Therefore, the intrinsic breakdown strengths of the low k dielectric layers are reduced due to the residual of the conductive metal ions, which degrades the electrical properties such as the voltage breakdown (Vbd) and the time dependent dielectric breakdown (TDDB) of the semiconductor devices with the low k dielectric layers. With the aggressive shrinkage of the interconnect pitch size in the chip, this problem becomes further exacerbated due to continuous technology scaling. Accordingly, improvements in methods of fabricating a semiconductor device with metal interconnections and corresponding designs of tools continue to be sought.